Electronic products are used in almost every aspect of life, and the heart of these electronic products is the semiconductor, or integrated circuit. Semiconductor devices are used in everything from airplanes and televisions to wristwatches.
Semiconductor devices are made in and on wafers by extremely complex systems that require the coordination of hundreds or even thousands of precisely controlled processes to produce a finished semiconductor wafer. Each finished semiconductor wafer has hundreds to tens of thousands of semiconductor dies, each worth as much as hundreds or thousands of dollars.
Semiconductor dies are made up of hundreds to billions of individual components. One common component is the transistor. The most common and important semiconductor technology presently used is silicon-based, and the most preferred silicon-based semiconductor technology is a Complementary Metal Oxide Semiconductor (CMOS) technology.
The principal elements of CMOS technology generally consist of a silicon substrate having trench isolation regions surrounding n-channel or p-channel transistor areas. The transistor areas contain polysilicon gates on a silicon oxide dielectric, or gate oxides, over the silicon substrate. The silicon substrate adjacently opposite the polysilicon gate is doped to become conductive. The doped regions of the silicon substrate are referred to as “shallow source/drain regions,” or “source/drain extension regions” which are separated by a channel region in the substrate beneath the polysilicon gate. An oxide or nitride spacer, referred to as a “sidewall spacer,” on the sides of the polysilicon gate allows deposition of additional doping to form more heavily doped regions of the shallow source/drain regions, which are called “deep source/drain regions.” The shallow and deep source/drain regions are collectively referred to as source/drain regions.
To complete the transistor, a dielectric layer is deposited to cover the polysilicon gate, the spacer, and the silicon substrate. To provide electrical contacts for the transistor, openings are etched in the dielectric layer to the polysilicon gate and the source/drain regions. The openings are filled with metal to form electrical contacts. To complete the integrated circuits, the contacts are connected to additional levels of wiring in additional levels of dielectric material to the outside of the dielectric material.
In operation, an input signal to the gate contact to the polysilicon gate controls the flow of electric current from one source/drain contact through one source/drain region through the channel to the other source/drain region and to the other source/drain contact.
Metal oxide semiconductor field effect transistor (MOSFET) devices are well known and widely used in the electronics industry. The carrier mobility of a MOSFET device is an important parameter because of its direct influence on the drive current and switching performance. In standard MOSFET technology, the channel length and gate dielectric thickness are reduced to improve current drive and switching performance. However, reducing the gate dielectric thickness can compromise device performance because of the associated increase in gate leakage current.
It has been shown that in p-channel MOSFETs, or pFETs, a buried silicon-germanium channel region under compressive stress enhances hole mobility in the channel region. Accordingly, a higher drive current can be obtained resulting in faster operating pFETs.
One existing strained channel silicon semiconductor includes strained silicon (Si) on a relaxed Silicon/Germanium (SiGe) substrate to obtain the stresses needed. However, these devices have the disadvantages of self-heating and a tight thermal budget window. A higher strain also is required for pFET transistors to obtain enhanced hole mobility.
One proposed solution involves etching a recess in the area of the source/drain regions and depositing SiGe or silicon/germanium/carbon (SiGeC) in the recess to strain the channel of the transistor. This method involves an additional etching step that adds to the cost of manufacturing the devices.
Another proposed solution involves forming germanium (Ge) on an insulator by oxidation of SiGe on an insulating material, such as an oxide. This approach employs Ge as the channel of the transistor. This approach requires an insulating layer that also adds to the cost of manufacturing the devices.
In the semiconductor industry, there has recently been a high-level of activity using strained Si-based heterostructures to achieve high mobility structures for CMOS applications. One method to implement this has been to grow strained Si layers on thick relaxed SiGe buffer layers.
Despite the high channel electron mobilities reported for heterostructures, the use of thick SiGe buffer layers has several noticeable disadvantages associated therewith. Thick SiGe buffer layers are not typically easy to integrate with existing Si-based CMOS technology. The defect densities are still too high for realistic VSLI (very large scale integration) applications. The nature of the existing systems precludes selective growth of the SiGe buffer layer so that circuits employing devices with strained Si, unstrained Si and SiGe materials are difficult, and in some instances, nearly impossible to integrate.
Furthermore, during the formation of the SiGe epitaxial layer in silicon-on-insulator (SOI) wafers, a thin layer of a Si seed layer is required after source drain reactive ion etch (RIE) to enable growth of the SiGe epitaxial layer. With this approach, controllability of the thickness of the Si seed layer is currently a major concern and this problem becomes even more prominent when the Si layer in SOI is further thinned down, e.g. in FDSOI.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.